1. Field of the Invention
The present invention relates to an information-handling apparatus having memory means, and more particularly, to a data processor, such as a microcomputer including a digital IC chip on which data processing circuitry and memory circuitry are integrated and coupled to each other by signal lines called a bus; or a computer system comprising one or more processor chips, memory chips, peripheral control chips, interface chips, and peripheral devices, which are all coupled by a bus cable.
2. Description of the Prior Art
In a microcomputer, an area on the digital IC chip occupied by signal lines (buses) provided for transferring information is predominantly large as compared with an area of active elements on that IC. For example, in the digital IC chip, the proportion occupied by signal lines is at least 50% or more of the chip area, and in some case is 70 to 80%. Moreover, in an IC which is to operate with high speed processing and high performance, the number of required signal lines is increased further. Since the signal lines must be formed so as not to cause undesired interference with active elements and other signal lines, the more active elements and the signal lines there are, the less freedom there is in bus layout design. Thus, layout of a circuit pattern on an IC chip becomes difficult.
This problem with signal line layout is also present in a computer system which requires a large number of bus cables for interconnecting the various chips and the peripheral devices.
Further, the above-mentioned problem severely occurs in a data processor of a serial bus coupling system, such as in a pipeline processor, in comparison with the data processor of a common bus coupling system. This is because the serial bus system requires many roundabout routes through which data are transferred.